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SM5330A
3-channel Video Filter with Built-in 4-system Switch
OVERVIEW
The SM5330A is a 4-system input switching 3-channel video filter with 5th-order lowpass filter built-in. The lowpass filter cutoff frequency range is 5MHz to 13MHz (SD mode) or 16MHz to 40MHz (HD mode), controlled using an I2C BUS*1. The lowpass filter enables the device to be utilized in the analog input stage of video signal equipment, functioning as an ADC system anti-aliasing filter for 480i to 1080i signal systems. The signal input type and input system switching, in addition to the cutoff frequency, can be controlled using the I2C BUS. The I2C BUS slave address is set using the ADS pin (3-state input), allowing a maximum of three SM5330A devices to be controlled simultaneously.
*1. I2C BUS is a registered trademark of Philips Electronics N.V.
FEATURES
I
PINOUT
(Top view)
IN1_3 IN1_2 IN1_1 VREF
I/O_1
25
36
35
34
33
32
31
30
29
28
27
I
26
I
I I I I
I I I
Supply voltages * Analog : 4.75 to 5.25V * Digital : 3.0 to 5.5V 4-system input switch function (3 channels) Lowpass filter function with 64-level cutoff frequency setting for each of SD/HD modes * Cutoff frequency range SD : 5MHz to 13MHz HD: 16MHz to 40MHz Video input pins can be independently set to synctip clamp/bias/direct inputs Output muting function 2 x 8-bit D/A converters built-in for control of arbitrary external circuits I2C BUS interface control * Slave address: 48h, 49h, 4Ah select (up to three devices can be used simultaneously, selected by ADS input) * Data transfer rate: fast mode (400kbit/s) compatible * Control register write function, status register read function Output gain: 6dB Operating ambient temperature range: -20 to 70C Package: 48-pin LQFP
IREF
GND
GND
VDD
SDA
ADS
SCL
IN1_L1 IN1_L2 IIN1_L3 IN1_SW IN2_1 IN2_2 IN2_3 VCC IN2_L1 IN2_L2 IN2_L3 IN2_SW
37 38 39 40 41 42 43 44 45 46 47 48
24 23 22 21 20 19 18 17 16 15 14 13
I/O_0 VCCD VCC OUT_1 GND OUT_2 VCC GND VCC OUT_3 GND YOUT
TEST 10
DAC_1 11
IN3_1
IN3_2
IN3_3
IN4_1
IN4_2
IN4_3
PACKAGE DIMENSION
(Unit: mm) Weight: 0.18g
0.35MAX
7.00 0.20
I I I I
HDTVs LCD TVs PDPs Projectors
9.00 0.20
APPLICATIONS
DAC_0
7.00 0.20 9.00 0.20
+ 0.20 1.50 - 0.10
0.17 0.05
1.00TYP
0.10 0.07
ORDERING INFORMATION
Device SM5330AF Package 48-pin LQFP
0.50
0.339TYP
GND 12
1
2
3
4
5
6
7
8
GND
GND
9
0.10 0.19 0.05
0.08 M
0.50 0.10
SEIKO NPC CORPORATION --1
0 to 10
SM5330A
BLOCK DIAGRAM
VDD
VCCD ADS
I/O_1 I/O_0
VCC VREF IREF
DAC_1
DAC_0
SDA SCL DGND
I C BUS I/F
2
Control Logic
Reference
DAC
DAC
IN1_L1 IN1_L2 IN1_L3 IN1_SW IN1_1 IN1_2 IN1_3 IN2_L1 IN2_L2 IN2_L3 IN2_SW IN2_1 IN2_2 IN2_3
Comparator
Bias /off
Bias /off
Clamp /Bias /off
6dB 5th order LPF OUT_1
CH-1
Bias /off
Bias /off
Clamp /Bias /off
6dB 5th order LPF OUT_2
Bias /off
Bias /off
Clamp /Bias /off
CH-2
IN3_1 IN3_2 IN3_3 6dB
Bias /off Bias /off Clamp /Bias /off
5th order LPF
OUT_3
IN4_1 IN4_2 IN4_3
0dB YOUT CH-3
TEST GND
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SM5330A
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name IN3_1 IN3_2 IN3_3 GND IN4_1 IN4_2 IN4_3 GND DAC_0 TEST DAC_1 GND YOUT GND OUT_3 VCC GND VCC OUT_2 GND OUT_1 VCC VCCD I/O_0 I/O_1 ADS SCL SDA VDD DGND IREF VREF GND IN1_1 IN1_2 IN1_3 I/O*1 I I I GND I I I GND O I O GND O GND O P GND P O GND O P P I/O I/O I I I/O P GND O O GND I I I A/D*2 A A A A A A A A A D A A A A A A A A A A A A D D D D D D D D A A A A A A Description System 3 channel 1 video signal input pin System 3 channel 2 video signal input pin System 3 channel 3 video signal input pin Analog ground pin System 4 channel 1 video signal input pin System 4 channel 2 video signal input pin System 4 channel 3 video signal input pin Analog ground pin DAC voltage output pin. Output voltage set using the I2C BUS. Test pin. Connect to ground for normal operation. DAC voltage output pin. Output voltage set using the I2C BUS. Analog ground pin Y signal output pin. The channel 3 video signal is output without filtering. Analog ground pin Channel 3 video signal output pin. The output system is selected using the I2C BUS. Analog supply pin Analog ground pin Analog supply pin Channel 2 video signal output pin. The output system is selected using the I2C BUS. Analog ground pin Channel 1 video signal output pin. The output system is selected using the I2C BUS. Analog supply pin Logic supply pin. Connect to the same potential as VCC. Logic I/O pins. Outputs are open-drain. Connect pull-up to VCCD. The open-drain outputs are turned ON/OFF using I2C BUS settings. The input state can be read out via the I2C BUS. Address select pin. 3-state input Select the I2C BUS slave address. (L: 48h, H: 49h, Z: 4Ah) I2C BUS clock signal pin. Connect pull-up to VDD. I2C BUS data signal pin. Connect pull-up to VDD. The output is open-drain. I2C BUS interface-stage supply pin. 3.0V to 5.5V Logic ground pin Cutoff frequency control pin. Connect a 1.8k 1% resistor between this pin and GND. The current that flows in the resistor sets the internal filter reference current. Internal reference voltage pin Analog ground pin System 1 channel 1 video signal input pin System 1 channel 2 video signal input pin System 1 channel 3 video signal input pin
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SM5330A
Number 37 38 39 40 41 42 43 44 45 46 47 48 Name IN1_L1 IN1_L2 IN1_L3 IN1_SW IN2_1 IN2_2 IN2_3 VCC IN2_L1 IN2_L2 IN2_L3 IN2_SW I/O*1 I I I I I I I P I I I I A/D*2 D D D D A A A A D D D D Description System 1 D-terminal signal discriminator input pin. 3-state input System 1 D-terminal signal discriminator input pin System 1 D-terminal signal discriminator input pin. 3-state input System 1 D-terminal signal discriminator input pin System 2 channel 1 video signal input pin System 2 channel 2 video signal input pin System 2 channel 3 video signal input pin Analog supply pin System 2 D-terminal signal discriminator input pin. 3-state input System 2 D-terminal signal discriminator input pin System 2 D-terminal signal discriminator input pin. 3-state input System 2 D-terminal signal discriminator input pin
*1. I: input, O: output, P: Power supply, GND: Ground *2. A: analog, D: digital
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SM5330A
PIN EQUIVALENT CIRCUITS
Number Name I/O*1 Equivalent circuit
34 35 36 41 42 43 1 2 3 5 6 7
IN1_1 IN1_2 IN1_3 IN2_1 IN2_2 IN2_3 IN3_1 IN3_2 IN3_3 IN4_1 IN4_2 IN4_3
VCC
I
45 INn_n
20k
GND
VCC
9 11
DAC_0 DAC_1
O
5k DAC_n
5k
GND
VCCD
10
TEST
I
180 TEST
GND
VCC
13
YOUT
O
200 YOUT
GND
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SM5330A
Number Name I/O*1 Equivalent circuit
VCC
OUT_n
15 19 21
OUT_3 OUT_2 OUT_1
O
GND 671
500
VCCD
24 25
I/O_0 I/O_1
I/O
180 I/O_n
DGND
VCCD
100k
26
ADS
I
180 ADS
100k
DGND
VDD
27
SCL
I
180 SCL
DGND
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SM5330A
Number Name I/O*1 Equivalent circuit
VDD
28
SDA
I/O
180 SDA
DGND
VCC
31
IREF
O
70 IREF 200
GND
VCC
32
VREF
O
VREF
GND
VCC
37 38 39 40 45 46 47 48
IN1_L1 IN1_L2 IN1_L3 IN1_SW IN2_L1 IN2_L2 IN2_L3 IN2_SW
I
180 INn_Ln
GND
*1. I: input, O: output
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SM5330A
SPECIFICATIONS
Absolute Maximum Ratings
GND = 0V, VCC = VDD = VCCD
Parameter Supply voltage Input voltage Storage temperature range Power dissipation Junction temperature Symbol VCC VIN TSTG PD TJ ja = 60C/W (at Ta = 25C, PCB wiring density: 100%, 0.5m/s air flow) Condition VCC, VDD, VCCD Rating -0.3 to 7.0 GND - 0.3 to VCC + 0.3 -55 to +125 0.91 125 Unit V V C W C
Recommended Operating Conditions
Parameter Supply voltage 1 Supply voltage 2 Operating ambient temperature Symbol VCC VDD Ta VCC, VCCD VDD Wiring density: 100%, air flow: 0.5m/s Condition Rating 4.75 to 5.25 3.0 to 5.5 -20 to 70 Unit V V C
Electrical Characteristics
DC Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8k, RL = 75k, CH-1 and CH-2 bias inputs, CH-3 clamp input, FCM = H, FCSET = 3Fh, unless otherwise noted.
Parameter Current consumption HIGH-level input voltage 1 LOW-level Input voltage 1 HIGH-level input voltage 2 Middle-level input voltage 2 LOW-level input voltage 2 HIGH-level input voltage 3 Middle-level input voltage 3 LOW-level input voltage 3 HIGH-level input voltage 4 LOW-level Input voltage 4 HIGH-level input voltage 5 LOW-level Input voltage 5 HIGH-level input voltage 6 LOW-level Input voltage 6 HIGH-level input leakage current 1 LOW-level input leakage current 1 HIGH-level input leakage current 2 LOW-level input leakage current 2 LOW-level output voltage Symbol ICC1 VIH1 VIL1 VIH2 VIM2 VIL2 VIH3 VIM3 VIL3 VIH4 VIL4 VIH5 VIL5 VIH6 VIL6 ILH1 ILL1 ILH2 ILL2 VOL IN1_L2, IN2_L2 IN1_L1, IN1_L3, IN2_L1, IN2_L3 ADS Condition VCC = 5.25V, VIN = 0.0VP-P SDA, SCL Rating min - 0.7 VDD - 0.8 VCC VCC/2 - 0.2 - 3.5 1.4 - 3.5 - 3.2 - 3.0 - - - - - 0.0 typ 112 - - - - - - - - - - - - - - - - - - - max 154 - 0.3 VDD - VCC/2 + 0.2 0.2 VCC - 2.4 0.8 - 2.4 - 1.8 - 1.5 1.0 1.0 1.0 1.0 0.4 Unit mA V V V V V V V V V V V V V V A A A A V Test level I I I I I I I I I I I I I I I I I I I I
IN1_SW, IN2_SW
I/O_0, I/O_1 SDA, SCL at input voltage = VDD SDA, SCL at input voltage = 0V I/O_0, I/O_1 at input voltage = VCC I/O_0, I/O_1 at input voltage = 0V SDA, I/O_0, I/O_1 at output current = 3mA
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SM5330A I2C BUS AC Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25C, unless otherwise noted.
Rating Parameter SCL clock frequency SCL hold time (start condition) SCL LOW-level clock pulsewidth SCL HIGH-level clock pulsewidth SCL setup time (start condition) SDA data hold time SDA data setup time SDA, SCL rise time SDA, SCL fall time SCL setup time (stop condition) Bus free time (stop condition to start condition) SDA, SCL input capacitance Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Ci Condition min 0 0.6 1.3 0.6 0.6 0 100 - - 0.6 1.3 - typ - - - - - - - - - - - - max 400 - - - - 0.9 - 300 300 - - 10 kHz s s s s s ns ns ns s s pF Unit Test level II II II II II II II II II II II II
SDA
tf
tLOW
tr
tr
tSU;DAT tf
tBUF
tHD;STA
SCL
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tSU;STO
S
Sr
Note. S, Sr: start condition, P: stop condition
P
Analog Input Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8k, RL = 75k, FCM = H, FCSET = 3Fh, unless otherwise noted.
Rating Parameter Clamp voltage Bias voltage Input resistance Input amplitude 1 Input amplitude 2 Input DC voltage range Symbol VCLAMP VBIAS RIBIAS VAI1 VAI2 VIDC Clamp input Bias input Bias input Clamp input, THD < 1.0% Bias input, THD < 1.0% Direct input Condition min 1.65 2.15 - - - 1.5 typ 1.85 2.35 20 - - - max 2.05 2.55 - 1.2 1.2 3.0 V V k Vp-p Vp-p V Unit Test level I I II I I I
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SM5330A Analog Output Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8k, RL = 75, FCM = H, FCSET = 3Fh, unless otherwise noted.
Rating Parameter Output gain Gain error between channels Output amplitude 1 Output amplitude 2 Crosstalk between channels Crosstalk between input systems Drive load resistance I2C response time Symbol AV dAV VOUT1 VOUT2 XTLKCH XTLKMUX RL tIIC Condition min OUT_1, OUT_2, OUT_3 Between OUT_1, OUT_2, and OUT_3 Clamp input, THD < 1.0% Bias input, THD < 1.0% 0.5Vp-p input, fin = 1MHz, between 2 channels 0.5Vp-p input, fin = 1MHz, between each input system OUT_1, OUT_2, OUT_3 Response time from ACK bit output when changing settings using I2C BUS 5.5 - - - - - 75 - typ 6.0 - - - -70 -70 - - max 6.5 0.2 2.4 2.4 - - - 1 dB dB Vp-p Vp-p dB dB s Unit Test level I I I I II II I II
Filter Frequency Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8k, RL = 75k, CH-1 and CH-2 bias inputs, CH-3 clamp input, unless otherwise noted.
Rating Parameter Symbol fC1 fC2 Cutoff frequency fC3 fC4 fC5 4fc attenuation ASB Condition min FCM = 0, FCSET = 00h FCM = 0, FCSET = 3Fh FCM = 1, FCSET = 00h FCM = 1, FCSET = 32h FCM = 1, FCSET = 3Fh fin = 4fc, attenuation from fin = 100kHz 4.50 11.71 13.74 30.96 - - typ 5.11 13.30 15.61 35.18 40.27 60 max 5.72 14.89 17.48 39.40 - - MHz MHz MHz MHz MHz dB Unit Test level I I I I II II
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SM5330A DAC Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25C, unless otherwise noted.
Rating Parameter Symbol Condition min DAC_0, DAC_1, Vn - Vn-1 (V191 - V63)/128 Vn: output voltage at resister value set "n" DAC HIGH-level output voltage DAC LOW-level output voltage DAC output current VOH-DAC VOL-DAC IO-DAC DAC_0, DAC_1, DAC0 = DAC1 = FFh DAC_0, DAC_1, DAC0 = DAC1 = 00h DAC0 = DAC1 = FFh 4.30 0.25 -0.5 4.45 0.35 - 4.60 0.45 +0.5 V V mA I I I typ max Unit Test level
Differential linearity
DLE
- 1, n = 1 to 255
-1
0
+1
LSB
I
Test Level The definition of "Test Level" shown in the electric characteristic table is as follows. I : 100% of products tested at Ta = + 25C. II : Guaranteed as result of design and characteristics evaluation. Measurement Circuit
VDD VCC 2.2k 2.2k
IN1_PR IN1_PB 75/50 75/50 75/50 IN1_Y
1F 1F 1F
SDA SCL
10k
1.8k1%
1F
10k
I/O_1 I/O_0 I/O_1 I/O_0 VCCD VCC OUT_1 GND OUT_2 VCC GND VCC OUT_3 75 75 GND DAC_0 DAC_1 75 1000F 0 OUT_Y 1000F 0 OUT_PB 1000F 0 OUT_PR YOUT GND YOUT SDA SCL TEST GND VDD ADS
IN1_3
IN1_2
IN1_1
VREF IN4_1
IN1_L1 IN1_L2 IN1_L3 IN1_SW IN2_PR IN2_PB 75/50 75/50 75/50 IN2_Y 1F 1F 1F
IN1_L1 IN1_L2
IIN1_L3 IN1_SW IN2_1 IN2_2 IN2_3 VCC IN2_L1 IN2_L2 IN2_L3 IN3_1 IN3_2 IN3_3 IN4_2 IN4_3 IN2_SW GND GND
IN2_L1 IN2_L2 IN2_L3 IN2_SW IN3_PR IN3_PB 75/50 75/50 75/50 IN3_Y 1F 1F 1F
IREF
GND
DAC_1 DAC_0
IN4_PR IN4_PB 75/50 75/50 75/50 IN4_Y
1F 1F 1F
Note. This is a circuit only for the evaluation board of an electric characteristics. (It is not a recommended application circuit.)
SEIKO NPC CORPORATION --11
SM5330A
FUNCTIONAL DESCRIPTION
I2C BUS Control
The SM5330A uses the I2C BUS interface to control the following functions: 1) Cutoff frequency setting 2) Input type switching (synctip clamp, bias, or direct mode) 3) Mute setting 4) Input switch select 5) I/O output settings 6) DAC output settings In addition, the interface is used to read the following status parameters: 7) I/O input state 8) D-terminal signal discrimination result The transfer rate is compatible with fast mode (400kbit/s). Basic Cycle The write sequence is: SM5330A slave address specific control register sub-address write data. Data can be written to the SM5330A in successive bytes, as the sub-address for the register is incremented automatically after each byte. However, if the sub-address exceeds the address of the last register (04h), data write operation to the SM5330A register stops and the acknowledge signal is not returned.
Single byte access
S Slave address A Sub address A Data A P
Multi byte access (address auto increment)
S Slave address A Sub address A Data A Data A
...
A
Data
A
P
S: START condition, P: STOP condition, A: acknowledge
: drive master device
: drive SM5330A
Figure 1. Write sequence The read sequence is: SM5330A slave address sub-address 0 status register value sub-address 1 status register value sub-address 2 status register value. Each read cycle comprises 3 bytes of read data. A specific status register sub-address cannot be assigned for a read operation.
Slave address Data #0 Data #1 Data #2
S
A
A
A
A
P
S: START condition, P: STOP condition, A: acknowledge
: drive master device
: drive SM5330A
Figure 2. Read sequence
SEIKO NPC CORPORATION --12
SM5330A Slave Address The 7-bit slave address is selected using the ADS pin. When ADS = "L" the address is 48h, when ADS = "H" the address is 49h, and when ADS = "Z" (open) the address is 4Ah. A maximum of three SM5330A devices can be connected to one I2C BUS simultaneously, and controlled independently by setting the slave address of each using the ADS pin.
SLAVE ADDRESS for control register write
bit7 Name 1 Value 1 1 0 0 0 0 0 0 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W 0 0 0 0 0 1 0 1 0 0 0 0 90h 92h 94h (Hex) SLAVE ADDRESS 1 1 1 Description Indicate to write when device's slave address is 48h (ADS = "L") Indicate to write when device's slave address is 49h (ADS = "H") Indicate to write when device's slave address is 4Ah (ADS = "Z")
SLAVE ADDRESS for status register read
bit7 Name 1 Value 1 1 0 0 0 0 0 0 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W 0 0 0 0 0 1 0 1 0 1 1 1 91h 93h 95h (Hex) SLAVE ADDRESS 1 1 1 Description Indicate to read when device's slave address is 48h (ADS = "L") Indicate to read when device's slave address is 49h (ADS = "H") Indicate to read when device's slave address is 4Ah (ADS = "Z")
Control Register The SM5330A has a 5-byte control register.
CONTROL REGISTER MAP
Addr. 00h 01h 02h 03h 04h - bit7 FCM IM1 INSEL DAC0 DAC1 bit6 - IM2 - bit5 bit4 bit3 bit2 bit1 bit0 Filter fc setting IM4 - I/O1 I/O0 Input mode setting Input switch select, I/O output control DAC_0 output control DAC_1 output control Description FCSET IM3
The function of each byte in the control register is described in the following tables.
SUB ADDRESS: 00h - Filter fc setting
bit7 Name default FCM 0 0 1 0 Value 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 : 1 1 1 0 0 0 : 1 0 1 0 1 0 0 0 0 00h : 3Fh 80h : BFh bit6 - 0 0 0 0 bit5 bit4 bit3 bit2 bit1 bit0 (Hex) FCSET 0 0 0 00h Set filter to SD mode (default) Set filter to HD mode fc = 5.11MHz (default) : fc = 13.30MHz fc = 15.61MHz : fc = 40.27MHz Description
Sets the cutoff frequency. When FCM = "0" the filter is set to SD mode, and when FCM = "1" the filter is set to HD mode. The relationship between the register value and the cutoff frequency is described in section "Lowpass Filter".
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SM5330A
SUB ADDRESS: 01h - Input mode setting
bit7 Name default 0 0 0 1 1 IM1 0 0 1 0 1 0 0 1 Value 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 bit6 bit5 IM2 0 0 bit4 bit3 IM3 0 0 bit2 bit1 IM4 0 00h IN1_3: synctip clamp input, IN1_2 and IN1_1: bias input (default) IN1_3, IN1_2 and IN1_1: bias input IN1_3, IN1_2 and IN1_1: synctip clamp input IN1_3, IN1_2 and IN1_1: direct (DC) input IN2_3: synctip clamp input, IN2_2 and IN2_1: bias input (default) IN2_3, IN2_2 and IN2_1: bias input IN2_3, IN2_2 and IN2_1: synctip clamp input IN2_3, IN2_2 and IN2_1: direct (DC) input IN3_3: synctip clamp input, IN3_2 and IN3_1: bias input (default) IN3_3, IN3_2 and IN3_1: bias input IN3_3, IN3_2 and IN3_1: synctip clamp input IN3_3, IN3_2 and IN3_1: direct (DC) input IN4_3: synctip clamp input, IN4_2 and IN4_1: bias input (default) IN4_3, IN4_2 and IN4_1: bias input IN4_3, IN4_2 and IN4_1: synctip clamp input IN4_3, IN4_2 and IN4_1: direct (DC) input bit0 (Hex) Description
Sets the video signal input pin operating mode.
SUB ADDRESS: 02h - Input switch select, I/O output control
bit7 Name default - 0 0 0 0 0 Value 0 0 0 0 0 1 0 1 1 1 1 bit6 bit5 INSEL 0 x 0 0 1 1 0 x 0 1 0 1 bit4 bit3 - 0 0 0 0 0 0 0 0 0 0 bit2 - 0 0 0 0 0 0 0 0 0 0 0 1 0 1 bit1 I/O1 1 bit0 I/O0 1 43h Mute IN1_n select (default) IN2_n select IN3_n select IN4_n select I/O_1 output "L" I/O_1 output off (input available) (default) I/O_0 output "L" I/O_0 output off (input available) (default) (Hex) Description
Sets the video signal input switching and logic I/O pin output settings. The input can be switched between 4 systems (3-channels). This setting also determines the system that performs status register D-terminal discrimination. The I/O_0 and I/O_1 pins are n-channel MOS open-drain outputs. When the I/O pins are used as inputs, these bits are set to "1" so that the output is high impedance.
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SM5330A
SUB ADDRESS: 03h - DAC_0 output control
bit7 Name default 0 0 Value 1 1 1 1 0 0 0 0 0 0 : 1 1 1 1 bit6 bit5 bit4 DAC0 0 0 0 0 0 0 0 0 00h 00h : FFh DAC_0 output 0.35V (default) : DAC_0 output 4.45V bit3 bit2 bit1 bit0 (Hex) Description
SUB ADDRESS: 04h - DAC_1 output control
bit7 Name default 0 0 Value 1 1 1 1 0 0 0 0 0 0 : 1 1 1 1 bit6 bit5 bit4 DAC1 0 0 0 0 0 0 0 0 00h 00h : FFh DAC_1 output 0.35V (default) : DAC_1 output 4.45V bit3 bit2 bit1 bit0 (Hex) Description
Sets the DAC_0 and DAC_1 pins output voltage, respectively. Status Register The SM5330A has a 3-byte status register.
STATUS REGISTER MAP
Addr. 00h 01h 02h - bit7 - bit6 - L1 - - - bit5 - bit4 - L2 - - bit3 - bit2 - bit1 IN1 L3 SW1 SW2 bit0 IN0 Description I/O input status D-terminal input status D-terminal connection status
The function of each byte in the status register is described in the following tables.
SUB ADDRESS: 00h - I/O input status
bit7 Name - 0 0 Value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 I/O_0 input "L" (< 1.5V) I/O_0 input "H" (> 3.0V) bit6 - 0 0 bit5 - 0 0 bit4 - 0 0 bit3 - 0 0 bit2 - 0 0 bit1 IN1 0 1 bit0 Description IN0 I/O_1 input "L" (< 1.5V) I/O_1 input "H" (> 3.0V)
Returns the input state of the logic I/O pins. The I/O_0 and I/O_1 pins are n-channel MOS open-drain outputs. When the I/O pins are used as inputs, set the outputs "1" (high impedance) in the control register.
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SM5330A
SUB ADDRESS: 01h - D-terminal input status
bit7 Name bit6 L1 bit5 bit4 L2 bit3 bit2 bit1 L3 Decode INn_Ln input selected series via INSEL register (L1: screen ruling) 0 0 1 Value 0 1 1 0 INn_L2 input "L" (< 2.4V) means "60i" INn_L2 input "H" (> 3.5V) means "60p" (L3: aspect ratio) 0 0 1 0 1 0 1 0 0 INn_L3 input "L" (< 0.8V) means "4 : 3" INn_L3 input "M" (1.4 to 2.4V) means "Letter Box" INn_L3 input "H" (> 3.5V) means "16 : 9" 0 1 0 1 0 0 INn_L1 input "L" (< 0.8V) means "480" INn_L1 input "M" (1.4 to 2.4V) means "720" INn_L1 input "H" (> 3.5V) means "1080" (L2: I/P) bit0 Description
Returns the D-terminal discrimination result for the system determined by the INSEL register.
SUB ADDRESS: 02h - D-terminal connection status
bit7 Name 0 0 Value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 IN2_SW input "L" (< 1.8V) means "connected" IN2_SW input "H" (> 3.2V) means "unconnected" 0 0 0 0 bit6 bit5 - 0 0 0 0 0 0 bit4 bit3 bit2 bit1 SW1 0 1 bit0 Description SW2 IN1_SW input "L" (< 1.8V) means "connected" IN1_SW input "H" (> 3.2V) means "unconnected"
Returns the D-terminal connection status information.
SEIKO NPC CORPORATION --16
SM5330A
Input Circuit
The SM5330A video input pin operating mode can be switched between synctip clamp, bias, and direct (without DC restore) modes for each channel. The possible combinations are described below (set independently for each system).
Table 1. Input mode combination
Control register IMn value 00 b 01 b 10 b 11 b INn_1 Bias Bias Clamp Direct Input mode INn_2 Bias Bias Clamp Direct INn_3 Clamp Bias Clamp Direct
The SM5330A has a 4-system input switch built-in, and the system selected by the control register INSEL bits is input to the lowpass filter. When muting is selected (INSEL = 000b), the signal is not input to the lowpass filter and the output pins are DC level.
SEIKO NPC CORPORATION --17
SM5330A
Lowpass Filter
The SM5330A has a 5th-order lowpass filter built-in, with a cutoff frequency selectable from 64 levels each for SD/HD mode controlled using the I2C BUS. The cutoff frequency settings are displayed graphically in figure 3, and shown in table 2.
50 45 40 35 fc [MHz] 30 25 20 15 10 5 0 0 32 64 96 128 160 192
Frequency [MHz]
Figure 3. FCSET setting vs. Cutoff frequency
Table 2. Cutoff frequency vs. FCDATA (RISET = 1.8k)
FCDATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FCDATA 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 FCSET (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F FCSET (hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F fc [MHz] 5.11 5.24 5.37 5.50 5.63 5.76 5.89 6.02 6.15 6.28 6.41 6.54 6.67 6.80 6.93 7.06 fc [MHz] 15.61 16.01 16.40 16.79 17.18 17.57 17.96 18.35 18.75 19.14 19.53 19.92 20.31 20.70 21.09 21.48 FCDATA 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FCDATA 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 FCSET (hex) 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F FCSET (hex) 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F fc [MHz] 7.19 7.32 7.45 7.58 7.71 7.84 7.97 8.10 8.23 8.36 8.49 8.62 8.75 8.88 9.01 9.14 fc [MHz] 21.88 22.27 22.66 23.05 23.44 23.83 24.22 24.62 25.01 25.40 25.79 26.18 26.57 26.96 27.36 27.75 FCDATA 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 FCDATA 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 FCSET (hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F FCSET (hex) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF fc [MHz] 9.27 9.40 9.53 9.66 9.79 9.92 10.05 10.18 10.31 10.44 10.57 10.70 10.83 10.96 11.09 11.22 fc [MHz] 28.14 28.53 28.92 29.31 29.70 30.10 30.49 30.88 31.27 31.66 32.05 32.44 32.84 33.23 33.62 34.01 FCDATA 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 FCDATA 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 FCSET (hex) 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F FCSET (hex) B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF fc [MHz] 11.35 11.48 11.61 11.74 11.87 12.00 12.13 12.26 12.39 12.52 12.65 12.78 12.91 13.04 13.17 13.30 fc [MHz] 34.40 34.79 35.18 35.58 35.97 36.36 36.75 37.14 37.53 37.92 38.32 38.71 39.10 39.49 39.88 40.27
SEIKO NPC CORPORATION --18
SM5330A
YOUT Pin
The YOUT pin is the unfiltered output of the selected system input pin (IN1_3, IN2_3, IN3_3, or IN4_3). The output gain is approximately 0dB.
IREF Pin
The IREF pin controls the built-in lowpass filter reference current, using a 1.8k 1% control resistor that must be connected. The current flows into the IREF pin in normal operating mode and during output muting.
VREF Pin
The VREF pin is the internal reference voltage output. It is recommended that a capacitor be connected between VREF and GND to ensure SM5330A operating stability. The recommended value is 1F. The voltage on VREF is output in normal operating mode and during output muting.
D-Terminal Discrimination Function
The D-terminal signal discrimination result can be read using the I2C BUS. The status register SW1 bit returns the state of IN1_SW, and the SW2 bit returns the state of IN2_SW. When IN1_n is selected by control register settings (INSEL = 100b), the status register L1, L2, L3 bits return the IN1_L1, IN1_L2, IN1_L3 pin states, respectively. Similarly, when IN2_n is selected (INSEL = 101b), the status register bits return the IN2_L1, IN2_L2, IN2_L3 pin states, respectively.
DAC
The SM5330A has two D/A converters controlled using the I2C BUS. The control register DAC0 bit controls the DAC_0 pin output voltage, and the DAC1 bit controls the DAC_1 output voltage.
I/O
The I/O_0 and I/O_1 I/O pins in output mode are n-channel MOS open-drain outputs. Connect pull-up resistance between respective pins and the VCCD pin. Recommendation value of pull-up resistance is 10k. When these pins are used as inputs, set the outputs "1" (high impedance) in the control register. When these pins are not used, they should have pull-up connections to VCCD or be connected to DGND.
Power-ON Reset
When power is applied, an internal power-ON reset circuit operates, initializing all internal register settings to their default settings. Power should be applied simultaneously on all supply pins.
SEIKO NPC CORPORATION --19
SM5330A
RECOMMENDED APPLICATION CIRCUIT
VDD VCC 2.2k 2.2k
IN1_PR IN1_PB IN1_Y 75 75 75
1F 1F 1F
SDA SCL
10k
1.8k1%
1F
10k
I/O_1 I/O_0 I/O_1 I/O_0 VCCD VCC OUT_1 GND OUT_2 VCC GND VCC OUT_3 75 75 GND DAC_0 DAC_1 75 1000F 75 OUT_Y 1000F 75 OUT_PB 1000F 75 OUT_PR YOUT GND YOUT SDA SCL TEST GND VDD ADS
IN1_3
IN1_2
IN1_1
VREF IN4_1
IN1_L1 IN1_L2 IN1_L3 IN1_SW IN2_PR IN2_PB IN2_Y 75 75 75 1F 1F 1F
IN1_L1 IN1_L2
IIN1_L3 IN1_SW IN2_1 IN2_2 IN2_3 VCC IN2_L1
IN2_L1 IN2_L2 IN2_L3 IN2_SW IN3_PR IN3_PB IN3_Y 75 75 75 1F 1F 1F
IN2_L2 IN2_L3 IN3_1 IN3_2 IN3_3 IN4_2 IN4_3 IN2_SW GND GND
IREF
GND
DAC_1 DAC_0
IN4_PR IN4_PB IN4_Y 75 75 75
1F 1F 1F
USAGE PRECAUTIONS
Supply Connections
Ensure that the VCC and VCCD have the same potential. VDD is the I2C BUS supply. The SCL and SDA signals should have a pull-up connection to VDD.
Setting the Slave Address to 49h
When the ADS pin is open-circuit, the slave address is set to 49h. When open, however, a large external spike noise or other interference can cause a malfunction. An external resistor should be connected to ADS as shown in figure 4 for protection.
29 VDD 10k 26 ADS 10k 30 VSS
Figure 4. Slave address 49h setting
SEIKO NPC CORPORATION --20
SM5330A
TYPICAL PERFORMANCE
VCC = 5.0V, VDD = 5.0V, Ta = 25C, VIN = 1.0Vp-p, RISET = 1.8k, RL = 75, unless otherwise noted.
12 Gain 0 -12 Gain [dB] -24 -36 -48 Group delay -60 0 10 20 30 40 50 Frequency [MHz] 0 -60 0 10 20 30 40 50 Frequency [MHz] 0 150 Group delay [ns] 120 90 60 30 180 12 0 -12 Gain [dB] -24 -36 -48 Group delay Gain 180 150 120 90 60 30 Group delay [ns] Group delay [ns]
Figure 5. Gain and Group delay characteristics (FCDATA = 0)
Figure 6. Gain and Group delay characteristics (FCDATA = 63)
12 Gain 0 -12 Gain [dB] -24 -36 -48 Group delay -60 0 10 20 30 40 50 Frequency [MHz]
180 150 Group delay [ns] 120 90 60 30 0
12 Gain 0 -12 Gain [dB] -24 -36 -48 -60 0 20 40 60 80 Frequency [MHz] Group delay
180 150 120 90 60 30 0 100
Figure 7. Gain and Group delay characteristics (FCDATA = 128)
Figure 8. Gain and Group delay characteristics (FCDATA = 191)
12 0 FCDATA = 191 -12 Gain [dB] FCDATA = 128 -24 -36 -48 -60 0 1.0 10.0 100.0 Frequency [MHz] FCDATA = 63 FCDATA = 0 Group delay [ns]
160 140 120 100 80 FCDATA = 63 60 40 20 0 0 20 40 60 80 100 Frequency [MHz] FCDATA = 128 FCDATA = 191 FCDATA = 0
Figure 9. Gain vs. FCDATA
Figure 10. Group delay vs. FCDATA
SEIKO NPC CORPORATION --21
SM5330A
Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter "Products") are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter "NPC"). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp
NC0501AE 2006.06
SEIKO NPC CORPORATION --22

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